1. Field of the Invention
This invention relates generally to apparatuses and methods for reading and writing data to a semiconductor memory arrays. More particularly, this invention relates to new and improved memory decoding propagation circuit design and configurations and data access methods to achieve shortened data cycle time to achieve high data access rate.
2. Description of the Related Art
Conventional technologies of data access for reading and writing data to memory arrays configured as multiple blocks are limited by the long cycle time due to the requirements of reading and writing larger arrays to achieve better area efficiency and faster access time and the latency in waiting for the global clock synchronization if synchronous pipeline structure is used for address decoding and data read and data write operations.
FIG. 1 shows a conventional multi-block or parallel memory structure, which comprises a block decoder circuit used to select one of the four sub-blocks. Each sub-block comprises a bit line decoder, a word line decoder, IO cells (sense amplifiers/write drivers), and a memory array. It should be mentioned that in a memory structure as shown in FIG. 1, the address decoder portion overall is an AND structure to perform the memory select function, and in the data output portion, the OR logic is implemented wherein OR devices or wired-OR connections are employed over multiple stages to perform the output data merging function. This multi-block memory structure are commonly implemented for each of the following memory types: SRAM, DRAM, ROM, PROM, EPROM, EEPROM, and FLASH.
For the purpose of optimizing a memory device design, it is more area efficient to have large memory arrays than having many smaller memory arrays, because large memory arrays require fewer interconnections, fewer decoders, and fewer IO circuits. However, large array requires more time to process the word line select, bit line select, bit line sensing, and bit line pre-charge. Therefore, larger array usually results in a longer cycle time. On the other hand, a memory device with larger array size have less number of blocks thus requiring less decoding time and tend to have better access time when compared with the access time of a memory device that has smaller size array but larger number of blocks. Therefore, there is no simple clear-cut solution to optimize the floor plan of a memory device. Depending on particular design requirements and the design specifications, in the process of designing a memory device, a designer is often required to trade off between the area and the access time to make a compromise.
Therefore, a need still exists in the art to provide an innovative configurations and method of circuit implementation for data access with significantly shortened cycle time without sacrificing much area costs such that the above discussed difficulties and limitations of the prior art technologies can be resolved.